PowerPro is the commercially available RTL sequential power optimization and power analysis tool. As a member of the PowerPro Product Validation team, you will be responsible for:
Role Responsibility /Requirement
Work as an integral part of R&D team to test PowerPro by creating new testcases in different Language (Verilog/VHDL/SV). Being the first customer of the tool, validate existing /new features and report bugs /enhancements. Suggest /implement measures to improve quality of product /test environment. Collaborate with various teams in order to make customer successful .Analyze customer reported bugs and plug gaps in testing, incorporate newer designs /flows. Use technical expertise to respond to customer inquiries, demonstrate products.
- B.Tech/M.Tech. in Electronics Engineering/VLSI.
- Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, Low Power concepts, low power tools, Verilog/VHDL/SV/RTL Simulation.
- Minimum 1-2 years’ experience in EDA.
- Knowledge of scripting languages like Perl/Tcl/Sed/Awk/Shell /Python will be a plus.
- Knowledge and experience using EDA tools like Real Time, Olympus, Questa, Conformal LP, Power-Artist, DC/RC, PT/PTPX, Incisive/VCS.
- Minimum understanding of low-power SOC design principles.
- Excellent verbal and written communication skills and a self-starter, motivated and strong team player.